In a known approach to network addressing, all stations on a network are assigned unique addresses. To this end, different blocks of addresses are assigned to different manufacturers, who are responsible for assigning specific addresses from their blocks to the products they manufacture. The assigned product addresses typically are stored in memories, usually read-only-memories ("ROM's"), on-board the products.
For example, for a bridge, each port to which an attachment can be connected is assigned an address from the manufacturer's block of addresses, and the central logic unit of the bridge often is assigned such an address as well. Each assigned address is unique on the networks connected to the bridge, and, of course, distinct from the other bridge addresses. The addresses assigned to the bridge ports each serve to identify the associated port, and accordingly is referred to as a "port address."
Typically, the physical addresses of the bridge ports and, if necessary, the central logic unit are stored in separate address memories in the bridge, for instance, in two or three separate ROM's implemented on two or three separate semiconductor chips. In other words, each address-ROM chip typically contains a single, unique address. This address is available for use, e.g., for communication purposes, provided, however, that it was accurately stored and is accurately recoverable.
Known address-ROM chips are carefully designed and manufactured so as to assure the accurate storage and recovery of address information specifying the assigned addresses. Consequently, the address information stored in such a chip typically includes redundant copies of the assigned address, and other data which, during data recovery, permits the detection of any errors in the stored information. Refined manufacturing techniques, including strict quality assurance procedures have been established by manufacturers of address-ROM chips to minimize the likelihood of manufacturing defects.
While such known addressing schemes have proven useful for their intended purposes, it would be desirable to provide more efficient approaches to the storage of the addresses assigned to a single product, i.e., approaches which preferably utilize fewer address-ROM chips while maintaining or improving the degree of flexibility, versatility and reliability presently realized by having each chip contain a single address. Not only would such approaches reduce the costs, space, and power consumption associated with the address-ROM chips themselves by requiring fewer in each product, but also of related hardware used in conjunction therewith. In addition, such new approaches preferably use the same or similar address-ROM chips as presently utilized so as to take advantage of the above-described chip fabrication techniques which have been so highly developed.